# debug

# create_debug_core u_ila_0 ila
# set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
# set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
# set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
# set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
# set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
# set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
# set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
# set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
# set_property port_width 1 [get_debug_ports u_ila_0/clk]
# connect_debug_port u_ila_0/clk [get_nets [list system_i/clk_wiz_0/inst/clk_50M]]
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
# set_property port_width 64 [get_debug_ports u_ila_0/probe0]
# connect_debug_port u_ila_0/probe0 [get_nets [list {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[0]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[1]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[2]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[3]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[4]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[5]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[6]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[7]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[8]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[9]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[10]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[11]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[12]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[13]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[14]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[15]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[16]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[17]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[18]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[19]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[20]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[21]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[22]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[23]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[24]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[25]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[26]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[27]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[28]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[29]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[30]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[31]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[32]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[33]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[34]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[35]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[36]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[37]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[38]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[39]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[40]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[41]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[42]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[43]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[44]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[45]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[46]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[47]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[48]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[49]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[50]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[51]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[52]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[53]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[54]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[55]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[56]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[57]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[58]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[59]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[60]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[61]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[62]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[63]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
# set_property port_width 32 [get_debug_ports u_ila_0/probe1]
# connect_debug_port u_ila_0/probe1 [get_nets [list {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[0]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[1]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[2]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[3]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[4]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[5]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[6]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[7]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[8]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[9]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[10]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[11]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[12]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[13]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[14]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[15]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[16]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[17]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[18]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[19]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[20]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[21]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[22]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[23]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[24]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[25]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[26]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[27]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[28]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[29]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[30]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[31]}]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
# set_property port_width 1 [get_debug_ports u_ila_0/probe2]
# connect_debug_port u_ila_0/probe2 [get_nets [list jtag_TCK_IBUF]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
# set_property port_width 1 [get_debug_ports u_ila_0/probe3]
# connect_debug_port u_ila_0/probe3 [get_nets [list jtag_TDI_IBUF]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
# set_property port_width 1 [get_debug_ports u_ila_0/probe4]
# connect_debug_port u_ila_0/probe4 [get_nets [list jtag_TDO_OBUF]]
# create_debug_port u_ila_0 probe
# set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
# set_property port_width 1 [get_debug_ports u_ila_0/probe5]
# connect_debug_port u_ila_0/probe5 [get_nets [list jtag_TMS_IBUF]]
# set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
# set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
# set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
# connect_debug_port dbg_hub/clk [get_nets clk]